This seminar introduces the use of FPGAs as a computation platform, and outlines techniques for mapping algorithms onto a hardware realisation. On this base, the parallelism inherent in hardware implementations can be used for accelerating the algorithms. Techniques for data-level and task-level parallelism are described, with examples drawn from image processing.

Biography

Donald Bailey has BE(Hons) (1982) and PhD (1985) degrees in Electrical and Electronic Engineering from University of Canterbury, New Zealand. He is a Senior Member of IEEE. Until 2024, he was Professor of Imaging Systems at Massey University, and director of the Centre for Research in Image and Signal Processing. Donald has spent over 40 years applying image processing technology to a range of industrial, machine vision and robot vision applications, and has spent the last 25 years researching in FPGA-based embedded image and signal processing systems. He is the author of over 300 publications in this field, including the book “Design for Embedded Image Processing on FPGAs”.